FINAL PROGRAM


Sunday, 12 July

Workshop Program

Workshop Chair: Randell Bramley


Monday, 13 July

Workshop Program

5:00

Early Registration

 

6.00

Cocktail Party

 


Tuesday, 14 July

8:00

Registration

 

9:00

Opening: The Right Honorable Alan Stockdale, State Treasurer and Minister for Multimedia

 

9:30

Keynote Speaker: Friedel Hossfeld, Central Institute for Applied Mathematics, Supercomputing Centre Research Centre, Juelich

 

 

The Value of Diversity: Meet the Need in CS&E

 

10:30

Break

 

11:00

Session 1A: High Performance Numerical Libraries

Session 1B: Architectural Resource Management 2.

 

Markus Hegland, Mike Osborne

Jose Gonzalez and Antonio Gonzalez

 

Algorithms for Block Bidiagonal Systems on Vector and Parallel Computers

The Potential of Data Value Speculation to Boost ILP

 

Peter Christen

Bryan Black, Brian Mueller, Stephanie Postal, Ryan Rakvie, Noppanunt Utamaphethai, John Paul Shen

 

A Parallel Iterative Linear System Solver with Dynamic Load Balancing

Load Execution Latency Reduction

 

R. Brent, L. Grosz, D. Harrar II, M. Hegland, M. Kahn, G. Keating, G. Mercer, O. Nielsen, M. Osborne, B. Zhou

Luis Villa, Roger Espasa, Mateo Valero.

 

Development of a Mathematical Subroutine Library for Fujitsu Vector Parallel
Processors

A Performance Study of Out-of-Order Vector Architectures and Short Registers

12:15

Lunch - Free Time

 

2:00

Session 2. Sparse Computation and Data Layout

 

 

Rong-Guey Chang, Tyng-Ruey Chuang, Jenq Kuen Lee

 

 

Efficient Support of Parallel Sparse Computation for Array Intrinsic Functions of Fortran 90

 

 

David A. Koufaty, Josep Torrellas

 

 

Comparing Data Forwarding and Prefetching for communication-induced Misses in Shared-Memory MPs

 

 

Dhruva R. Chakrabarti, Nagaraj Shenoy, Alok Choudhary, Prithviraj Banerjee

 

 

An Efficient Uniform Run-time Scheme for Mixed Regular-Irregular Applications

 

 

M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, J. Ramanujam

 

 

A Hyperplane Based Approach for Optimizing Spatial Locality in Loop Nests

 

3:40

Break

 

4:00

Session 3A. Speculative Execution

Session 3B. Compilation Technology

 

Pedro Marcuello, Antonio Gonzalez and Jordi Tubulla

Siegfried Benkner, Piyush Mehrotra, John Van Rosendale, Hans Zima

 

Speculative Multithreaded Processor

High-Level Management of Communication Schedules in HPF like languages

 

Venkata Krishnan and Josep Torrellas

Thomas Fahringer, Eduard Mehofer

 

Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor

Problem and Machine Sensitive Communication Optimization

 

Iffat H.Kazi and David J. Lilja

Gerald Roth, Ken Kennedy

 

Coarse-Grained Speculative Execution in Shared-Memory Multiprocessors

Loop Fusion in High Performance Fortran

 

Pritpal S. Ahuja, Kevin Skadron, Margaret Martonosi, Douglas W. Clark

M.Jimenez, J.M.Llaberta,A.Fernandez,E.Morancho

 

Multi-Path Execution: Opportunities and Limits

A General Algorithm for Tiling at the Register Level

5:40

Free Time

 

6:00 - 8.00 pm

State Reception and Cocktail Party, Proudly Supported by State Government of Victoria

 


Wednesday 15 July

8:30

Session 4A. Metacomputing and Cluster-Based Applications.

Session 4B. Compilation Technology.

 

Neil Spring, Rich Wolski

Francois Bodin, Yann Mevel, Rene Quiniou

 

Application Level Scheduling of Gene Sequence Comparison on Metacomputers

A User Level Program Transformation Tool

 

Kimura and H.Takemiya

William M Pottenger

 

Local Area Metacomputing for Multidisciplinary Problems: A Case Study for Fluid/Structure Co Simulation

The Role of Associativity and Commutativity in the Detection and transformation of loop level parallelism.

 

Dingchao Li, Akira Mizuno, Yuji Iwahori, Naohiro Ishii

Weng-Long Chang, Chih-Ping Chu

 

Exploiting Hetrogeneous Parallelism in the Presence of Communication Delays

The Infinity Lambda Test

 

Jorg Henrichs

Sungdo Moon, Mary Hall and Brian Murphy

 

Optimizing and Load Balancing Metacomputing Applications

Predicated Array Data-Flow Analysis for Run-Time
Parallelization

 

Cosimo Anglano

Byoungro So, Sungdo Moon, Mary W. Hall

 

Predicting Parallel Applications Performance on Non-dedicated
Cluster Platforms

Measuring the Effectiveness of Automatic Parallesisation in SUIF

10:35

Break

 

11:00

Keynote: Ian Foster - Argonne National Laboratories

 

 

Future Supercomputers: Supernodes for the Grid

 

12:00

Lunch - Free Time

 

2:00

Session 5. Distributed Software Structures.

 

 

Maciej Brodowicz and Olin Johnson

 

 

PARADISE: An Advanced Featured Parallel File System.

 

 

Jan-Jan Wu, Pangfeng Liu

 

 

Distributed Data Structure Design for Scientific Computation

 

 

Lars Lundberg, Daniel Hoggander

 

 

Bounding on the Gain of Optimizing Data Layout in Vector Processors

 

3:15

Break

 

3:45

Winery Tour & Conference Dinner </

 


Thursday 16 July

8:30

Session 6A. Software Support for Memory Hierarchy Management

Session 6B. Parallel Applications and Algorithms

 

Francis O'Carroll, Hiroshi Tezuka, Atsushi Hori and Yutaka Ishikawa

Paul D. Coddington and S.H. Ko

 

The Design and Implementation of Zero Copy MPI Using Commodity Hardware with a High Performance Network

Techniques for Empirical Testing of Parallel Random Number Generators

 

Cheng Liao, Dongming Jiang, Liviu Iftode, Margaret Matonosi, Douglas W. Clark

Alexis Vartanian, Jean-Luc Bechennec, Nathalie Drach-Temam

 

Monitoring Shared Virtual Memory Performance on a Myrinet-based PC Cluster

Evaluation of High Performance Multicache Parallel Texture Mapping

 

Takashi Matsumoto, Kei Hiraki

V. Krishnaswamy, P. Banerjee

 

MBCF: A Protected and Virtualized High-Speed User-Level Memory-Based Communication Facility

Parallel Compiled Event Driven VHDL Simulation

 

Osamu Tatebem, Yuetsu Kodama, Satoshi Sekiguchi, Yoshimori Yamaguchi

Andrew Sohn, Yuetsu Kodama

 

Highly Efficient Implementation of MPI Point-to-Point Communication Using Remote Memory Operations

Load Balanced Parallel Radix Sort

 

Angelos Bilas, Liviu Iftode, Jaswinder Pal Singh

Kenji Suehiro, Hitoshi Murai, Yoshiki Seo

 

Evaluation of Hardware-Support for Next Generation Shared Virtual Memory Clusters

Integer Sorting on Shared-Memory Vector Parallel Computers

10:35

Break

 

11:00

Keynote: Kei Hiraki, Tokyo University

 

 

Speculative Execution Model with Duplication

 

12:00

Lunch - Free Time

 

2:00

Session 7A. Multithreaded Systems

Session 7B. Prefetching

 

Suvas Vajracharya, Dirk Grunwald

Mattias M. Muller, Thomas M. Warschko, Walter F. Tichy

 

Dependence Driven Execution for Multiprogrammed Multiprocessors

Prefetching on the Cray-T3E

 

Eleftherios D. Polychronopoulos, Xavier Martorell, Dimitrios S. Nikolopoulos, Jesus Labarta

P. Ibanez, V. Vinals, J.L. Briz and M.J. Garzaran

 

 

Characterization and Improvement of Load/Store Cache-based Prefetching

 

Theodore S. Papatheodorou, Nacho Navarro

Chi-Hung Chi,Chi-Ming Cheung

 

Kernel-Level Scheduling for the Nano--Threads Programming Model.

Hardware-Driven Prefetching for Pointer Data References

 

Jeong-Si Kim, Young-Kee Jun

Ricardo Bianchini, Raquel Pinto and Claudio L. Amorim

 

Scalable On-the-fly Detection of the First Races in Parallel Programs

Data Prefetching for Software DSMs

 

Gabriel Rivera, Chan-Wen Tseng

 

 

Eliminating Conflict Misses for High Performance Architectures

 

3:40

Break

 

4:00

Session 8. Interconnection Networks

 

 

Yomin Hou, Chien-Min Wang, Lih-Hsing Hsu

 

 

Depth Contention-Free Broadcasting on Torus Networks

 

 

Enrique V. Carrera, Ricardo Bianchini

 

 

OPTNET: A Cost Effective Optical Network for Multiprocessors

 

 

C. Izu, A . Arrubarrena

 

 

Applying Segment Routing to k-ary n-cube Networks

 

 

Sajal Das, Daniel Harvey, and Rupak Biswas

 

 

Dynamic Load Balancing for Adaptive Meshes using Symmetric Broadcast Networks

 

4:40

Free Time

 

6:30

Yarra River and Inner Harbour Boat Cruise including Buffet Dinner

 


Friday 17 July

9:00 

Mateo Valero, University Poltecnica de Catalunya, Spain 

 

Vector Architectures: Past, Present and Future

 

10:00

Break

 

10:30

Session 9. Architecture.

 

 

Rakefet Kol and Ran Ginosar

 

 

Kin : A High Performance Asynchronous Processor Architecture

 

 

David Lopez, Josep Llosa, Mateo Valero, Eduard Ayguade

 

 

Resource Widening Versus Replication: Limits and Performance - Cost Trade-Off

 

 

Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson

 

 

Utilizing Reuse Information in Data Cache Management

 

 

Stefanos Kaxiras, Stein Gjessing, James R. Goodman

 

 

A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-Memory Multiprocessors

 

12:10

Closing Address

 

12:30

Conference Closes

 

 


Last updated 12 June 1998
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