20th ACM International Conference on Supercomputing


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A Modern High-Performance Processor Pipeline

Dr. Marc Tremblay
Sun Fellow, Vice President, and Chief Architect Scalable Systems Group
Sun Microsystems, Inc.

The traditional balance between processor clock rate and instruction level parallelism (ILP) has been
severely shaken due to enablers and constraints that were not prevalent or did not exist during the last two decades.

With the current broad deployment of multithreaded software for servers (increasing rapidly for desktops), a traditional processor, e.g. with high frequency and traditional OoO scheduling, is no longer optimal
to extract performance. Moreover as cache footprints grow due to problem size, scaling, and multiprogramming,
the memory wall problem is only getting worse. Not to be forgotten is Amdahl's law, which in this context of,
on-chip closely-coupled parallel execution, makes single-thread performance important since even a small fraction of non-scalable code affects overall performance.

Other constraints such as power density and overall power limitation for air- and liquid-cooled systems make putting multiple traditional
cores on a single die an unattractive design point.

High-Performance Throughput Computing, achieved through design-from-scratch processors composed of multiple multi-threaded cores, offers an unprecedent opportunity to create a new generation pipeline that delivers both high throughput performance and high single-thread performance.

This is the first disclosure of what we believe is the first truly new pipeline in a decade. A checkpoint-based
architecture that offers a new execution model will be described. Hardware threads are spawned and they speculatively execute and retire instructions out-of-order. Power efficiency is emphasized by maximizing the utilization of pipeline stages through temporal threading and functional units through spatial threading and speculation. This pipeline is embedded multiple times in our future high-end 65nm and 45nm processors that form the cornerstone a broad line of systems ranging from small servers to supercomputers.


Quantum Mechanical Approaches to Information Processing

Professor Steven Prawer
University of Melbourne Centre of Excellence for Quantum Computer Technology, Microanalytical Research Centre, School of Physics, University of Melbourne


Unless new paradigms can be developed for information processing the end is in sight for Moore’s Law which has guided the development of the computer industry for nearly half a century. One such paradigm shift is to design and engineer a new generation of algorithms and devices which exploit fundamental quantum mechanical properties such as quantum superposition and entanglement for both information processing and transmission. Entanglement offers the possibility of enormous speed up due to massively parallel operation. However, this requires new ways of thinking regarding the very nature of information processing in which measurement and read-out are intrinsic to successful quantum algorithms. For transmission of information, quantum superposition offers the possibility of communications whose absolute security is guaranteed by the laws of quantum mechanics.
But how close are we to being able to translate this potential into practical machines? The technical challenges are formidable because these devices need to control and manipulate individual atoms, electrons or photons. Nevertheless impressive progress has been made over the past five years. The very simplest devices which involve only one or two active quantum bits (qubits) are already finding application in ultra-secure communications systems using quantum key distribution. This requires a single photon source (i.e. a source that produces one and only one photon per pulse) and we will review our progress in fabricating such sources based on advanced diamond technology. Scaling up to many qubit architectures is even more challenging, but highly sophisticated devices which operate at the single electron level have recently been demonstrated. These devices represent the basic building blocks for a quantum information processor which, when integrated, may from the basis of practical quantum computing machines. In this talk, I will attempt to show how recent progress provides a glimpse into one possible version of tomorrow’s computing world.


Prof. Steven Prawer
University of Melbourne Centre of Excellence for Quantum Computer Technology, Microanalytical Research Centre
School of Physics Phone: + 61 (0)3 8344 5460
University of Melbourne Fax: + 61 (0)3 9347 4783
Victoria 3010 Email:

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